FIG. 1 illustrates an exemplary integrated circuit CI comprising an MOS transistor T according to the prior art.
The MOS transistor T is produced on and in an active zone ZA surrounded by an insulating region 1, for example of the shallow trench type (“Shallow Trench Isolation”, STI).
The active zone ZA comprises a doped drain region 2 and a doped source region 4 which are separated by a channel region 3 and made in a semi-conducting substrate.
The transistor T also comprises an insulated gate region 5 isolated from the active zone by a silicon oxide layer 6 (gate oxide).
In a conventional manner the drain, source and gate regions are silicided to allow contact pickups D, S, G on these regions.
The gate has a length L, extending in the source-drain direction, and this length can be equal to the technological node used for the production of an integrated circuit incorporating this transistor. Thus in a 40-nm technology, the length L can equal 40 nm.
The gate region 5 which extends transversely to the source-drain direction overlaps two opposite edges BD1 and BD2 of the active zone ZA at the level of two overlap zones ZCH1 and ZCH2, respectively.
At the level of the edges BD1 and BD2, the profile of the active zone exhibits a hump and a hollow.
This results in a non-uniform thickness of the gate oxide 6 in the overlap zones.
Moreover, in the active zone, in the neighborhood of the insulating region 1, the source side and drain side concentration of dopants is generally different from that situated at the center of the active zone, the reason for this being, inter alia, partial absorption of the dopants by the insulating region 1 during the implantation and diffusion of these dopants. Such is the case, for example, for boron used as dopant in nMOS transistors.
Such is also the case, but generally to a lesser extent, for the dopants of pMOS transistors.
It follows from this that parasitic transistors TP1 and TP2 are formed at the edges BD1 and BD2 of the active zone. More precisely the parasitic transistor TP1 possesses a part 20 of the drain region 2 and a part 40 of the source region 4 that are situated at the edge of the active zone ZA and a part 50 of the gate region 5 overlapping the edge BD1.
The parasitic transistor TP2 possesses a part 21 of the drain region 2 and a part 41 of the source region 4 that are situated at the edge of the active zone ZA and a part 51 of the gate region 5 overlapping the edge BD2.
These parasitic transistors, at the active zone edge, are shown schematically in FIG. 2 in which a central transistor T1, which is presumed to have the desired characteristics of the transistor T, has also been shown schematically.
The parasitic transistors TP1 and TP2 have a threshold voltage Vtp that is less than that of the central transistor T1. As the threshold voltage Vtp of the parasitic transistors is lower than that of the central transistor, the threshold voltage of the transistor T is de facto lower than that expected.
This effect is known in the prior art as the “hump effect”.
A known scheme of the prior art making it possible to circumvent the hump effect provides for a modification of the transistor in such a way that its gate is of octagonal shape. FIG. 3 illustrates an integrated circuit CI1 comprising such a transistor T2. The drain D is then situated in the middle of the octagon.
However, this architecture of the transistor exhibits the drawback of increasing the size of the transistor. The surface area occupied by the transistor is more than doubled with respect to a transistor of conventional shape in comparable technology.
A need consequently exists to cancel or at least to reduce the “hump” effect while retaining the standard size of the transistor for a given technology, doing so by modifying only summarily the method for fabricating transistors.